Semiconductor integrated circuit

ABSTRACT

In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.

This application is a continuation of application Ser. No. 739,424,filed on Aug. 2, 1991, now abandoned, which is a continuation of Ser.No. 520,620 filed on May 8, 1990, now U.S. Pat. No. 5,042,010 which is acontinuation of Ser. No. 358,262 filed on May 30, 1989, now U.S. Pat.No. 4,924,439, which is a continuation of Ser. No. 121,914 filed on Nov.17, 1987, now U.S. Pat. No. 4,858,189, which is a continuation of Ser.No. 701,226 filed on Feb. 13, 1985, now U.S. Pat. No. 4,713,796.

FIELD OF THE INVENTION

The present invention relates to a semiconductor integrated circuit inwhich memory cells are integrated on a large scale.

BACKGROUND OF THE INVENTION

A well-known type of semiconductor integrated circuit in which memorycells are integrated on a large scale (hereinbelow termed the"semiconductor memory") is the so-called RAM. The RAM (random accessmemory) is a device capable of storing information temporarily andreading it out when required. This type of memory is also called a"read/write memory".

Typically, a RAM includes memory cells which store information, anaddress circuit which externally selects a specified memory cell, and atiming circuit which controls the reading and writing of information.

In a RAM, a plurality of memory cells are arranged in the shape of amatrix. The operation of selecting a desired memory cell from among theplurality of memory cells is performed by selecting an intersectionpoint in the matrix. The access time is therefore constant irrespectiveof the position (addresses) of the selected memory cells within thematrix.

RAMs are broadly classified into two sorts; bipolar RAMs and MOSRAMs.

The bipolar RAM has the following merits:

(1) As compared with the MOSRAM, it operates faster.

(2) The operation of the memory cell is of the static type, and thecontrols of timings, etc. are simple.

On the other hand, the bipolar RAM has the following demerits:

(3) As compared with the MOSRAM, it exhibits a higher power consumption(especially when it does not operate).

(4) As compared with the MOSRAM, it requires a more complicatedmanufacturing process and is more difficult to attain a high density ofintegration.

Bipolar RAMs are presently generally classified into the two types ofthe TTL type and the ECL type, depending upon differences ininput/output levels. The access time (reading time) of the bipolar RAMof TTL interface falls within a range of 30-60 (nsec.), while the accesstime of the bipolar RAM of ECL interface falls within a range of 4-35(nsec.).

Accordingly, bipolar RAMs are applied to various memory systems wherehigh speed operations are required.

Meanwhile, when compared with the bipolar RAM, the MOSRAM is simpler instructure and in the manufacturing process. It is also more advantageousin terms of power consumption, storage density and price. Therefore, itis used in fields which do not require high speed operations.

MOSRAMs are classified into the dynamic type and the static type.

The dynamic type MOSRAM has its memory cell composed of a comparativelysmall number of transistors, namely, 1-3 transistors per bit (1-3transistors/bit). With an identical chip area, therefore, the bitdensity becomes higher than that of the static type MOSRAM to bedescribed later.

In the dynamic MOSRAM, information is stored as charges in a capacitancewithin the memory cell. Since the charges stored in the capacitance aredischarged due to a leakage current, etc., the information of the memorycell needs to be read out within a predetermined period of time and tobe rewritten again (i.e., refreshed).

On the other hand, in the static MOSRAM, a flip-flop circuit which isusually composed of 6 elements is used as the memory cell. For thisreason, the refresh which is required in the dynamic MOSRAM is notnecessary.

The access time of the dynamic MOSRAM falls within a range of 100-300(nsec.), while the access time of the static MOSRAM falls within a rangeof 30-200 (nsec.). Thus, it can be seen that the access time of theMOSRAM is a larger value when compared with that of the bipolar RAM.

Meanwhile, owing to improvements in photolithographic technology,reduction in the element dimensions of MISFETs within a semiconductorintegrated circuit has been promoted. In IEEE Journal of Solid-StateCircuit, Vol. SC-17, No. 5, pp. 793-797, issued in October 1982, thereis contained a static MOSRAM of 64 kbits which employs wafer processingtechniques based on design rules of 2 (μm) and which exhibits an accesstime of 65 (nsec.), an operating power consumption of 200 (mW) and astand-by power consumption of 10 (μW).

Meanwhile, as an example of the bipolar RAM of the ECL type, an ECL typebipolar RAM of 4 kbits which exhibits an access time of 15 (nsec.) and apower consumption of 800 (mW) is manufactured and sold by Hitachi, Ltd.under the product name "HM100474-15".

As explained above, there has been a definite technical trend to enlargethe storage capacity of semiconductor memories which has taken place inthe increments of 1 kbit, 4 kbits, 16 kbits, 64 kbits, 256 kbits, 1Mbit, . . . , quite independently of the features of the bipolar RAM ofhigh speed and high power consumption and the features of the MOSRAM oflow speed and low power consumption.

At the present time, when the power consumption of the semiconductormemory and the present-day photolithographic techniques determining theelement dimensions of bipolar transistors are taken into consideration,the storage capacity of the bipolar RAM will be limited to 16 kbits.

Meanwhile, with the enlargement of the storage capacity of thesemiconductor memory (particularly, at and above 64 kbits), the area ofa semiconductor chip increases, and the signal line of the addresscircuit of the RAM is arranged over a long distance on the semiconductorchip of large area. When the length of the signal line of the addresscircuit lengthens, naturally the stray capacitance of the signal lineincreases, and also the equivalent distributed resistance of the signalline increases. When, for the purpose of microminiaturization, thewiring width of the signal line of the address circuit is established as2 (μm) or less by improving photolithography, the equivalent distributedresistance of the signal line increases more. In addition, since thefan-out of each circuit enlarges with the increase of the storagecapacity, a load capacitance attributed to the gate capacitance of aMOSFET at the succeeding stage becomes high. Accordingly, in the 64-kbitMOSRAM which employs the photolithography of 2 (μm) and whose addresscircuit is entirely constructed of CMOSFETs, the access time ofaddresses will be limited to 30 (nsec.).

The present invention has been made by the inventors in developing asemiconductor memory which has an access time equivalent to that of anECL type bipolar RAM and a power consumption equivalent to that of astatic MOSRAM.

OBJECTS OF THE INVENTION

An object of the present invention is to provide a semiconductor memoryof high speed and low power consumption.

The above and other objects and novel features of the present inventionwill become apparent from the description of the specification and theaccompanying drawings.

SUMMARY OF THE INVENTION

An outline of a typical embodiment disclosed in the present applicationto achieve the above and other objects will be briefly explained below.

In an address circuit, a timing circuit, etc. within a semiconductormemory, an output transistor for charging and discharging a signal lineof relatively great length and an output transistor of large fan-out areconstructed of bipolar transistors. On the other hand, logic circuitsfor executing logic processing, for example, inversion, non-inversion,NAND and NOR operations are constructed of CMOS circuits.

The logic circuit constructed of the CMOS circuit has low powerconsumption, and the output signal of this logic circuit is transmittedto the signal line of relatively great length through the bipolar outputtransistor of low output impedance. Since the output signal istransmitted to the signal line by the use of the bipolar outputtransistor having low output impedance, the dependence of the signalpropagation delay time upon the stray capacitance of the signal line canbe diminished. Therefore, using the arrangement of the presentinvention, the object of providing a semiconductor memory of low powerconsumption and high speed can be achieved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B show a block diagram showing the internal arrangement ofa static RAM according to one embodiment of the present invention;

FIGS. 2A and 2B show a block diagram showing an address buffer ADB androw decoders R-DCR0, R-DCR1, R-DCR2 in FIG. 1 in greater detail;

FIGS. 3A and 3B show a block diagram showing the address buffer ADB, acolumn decoder C-DCR1, etc. in FIG. 1 in greater detail;

FIG. 4 is a circuit diagram showing a quasi-CMOS non-inverting/invertingcircuit for use in the present invention;

FIG. 5 is a circuit diagram showing a quasi-CMOS 3-input NAND circuitfor use in the present invention;

FIG. 6 is a circuit diagram showing a pure CMOS 3-input NAND circuit foruse in the present invention;

FIG. 7 is a circuit diagram showing a quasi-CMOS 2-input NOR circuit foruse in the present invention;

FIG. 8 is a circuit diagram showing a pure CMOS 2-input NOR circuit foruse in the present invention;

FIG. 9 is a circuit diagram showing a pure CMOS 2-input NAND circuit foruse in the present invention;

FIG. 10 is a circuit diagram showing a quasi-CMOS inverter for use inthe present invention;

FIGS. 11A and 11B show a circuit diagram showing a sense amplifierselector circuit SASC and an internal control signal generator circuitCOM-GE in FIG. 1 in greater detail;

FIG. 12 is a circuit diagram showing a sense amplifier SA1, a dataoutput intermediate amplifier DOIA, a data output buffer DOB, etc. inFIG. 1 in greater detail;

FIG. 13 is a circuit diagram showing a data input buffer DIB, a datainput intermediate amplifier DIIA1, etc. in FIG. 1 in greater detail;and

FIG. 14 is a diagram of the signal waveforms of the various parts of thestatic RAM of the embodiment shown in FIGS. 1 to 13, in a read cycle anda write cycle.

DETAILED DESCRIPTION

Now, an embodiment of the present invention will be described withreference to the drawings.

FIG. 1 shows the internal arrangement of a static RAM which has astorage capacity of 64 kbits and the input/output operation which isexecuted in single bit units. Various circuit blocks enclosed with abroken line IC are formed in a single silicon chip by semiconductorintegrated circuit technology.

The static RAM of the present embodiment includes four matrices (memoryarrays M-ARY1 to M-ARY4) each having a storage capacity of 16 kbits(=16384 bits), thereby to have a total storage capacity of 64 kbits(more specifically 65536 bits). The four memory arrays M-ARY1 to M-ARY4have arrangements similar to each other, and each of them has memorycells arranged in 128 rows×128 columns.

An address circuit for selecting a desired memory cell from the memoryarrays each having the plurality of memory cells is constructed of anaddress buffer ADB, row decoders R-DCR0, R-DCR1 and R-DCR2, columndecoders C-DCR1 to C-DCR4, column switches C-SW1 to C-SW4, etc.

Although not especially restricted, a signal circuit which handles thereading and writing of information is constructed of a data buffer DIB,data input intermediate amplifier D-IIA1-D-IIA4, a data output bufferDOB, a data output intermediate amplifier DOIA, and sense amplifiersSA1-SA16.

Although the invention is not especially restricted thereto, a timingcircuit for controlling the operations of reading and writinginformation is constructed of an internal control signal generatorcircuit COM-GE and a sense amplifier selector circuit SASC.

A decode output signal which is obtained on the basis of address signalsA₀ -A₈ is transmitted from the row decoder R-DCR1 or R-DCR2 to any ofrow-group address selection lines (word lines WL11-WL1128, WL21-WL2128,WR11-WR1128 and WR21-WR2128). Among the address signals A₀ -A₈, those A₇and A₈ are used for selecting one memory matrix from among the fourmemory matrices M-ARY1 to M-ARY4.

The address buffer ADB receives the address signals A₀ -A₁₅, and formsinternal complementary address signals a₀ -a₁₅ based on them. Theinternal complementary address signal a₀ is composed of an internaladdress signal a₀ which is inphase with the address signal A₀, and aninternal address signal a₀ whose phase is inverted to that of theaddress signal A₀. The remaining internal complementary address signalsa₁ -a₁₅ are similarly composed of internal address signals a₁ -a₁₅ andinternal address signals a₁ -a₁₅.

Among the internal complementary address signals a₀ -a₁₅ formed by theaddress buffer ADB, those a₇, a₈ and a₉ -a₁₅ are supplied to the columndecoders C-DCR1 to C-DCR4. The column decoders C-DCR1 to C-DCR4 decodethese internal complementary address signals, and supply selectionsignals (decode output signals) obtained by the decoding, to the gateelectrodes of switching insulated-gate field effect transistors(hereinbelow termed "MISFETs") Q₁₀₀₁, Q₁₀₀₁, Q₁₁₂₈, Q₁₁₂₈, Q₂₀₀₁, Q₂₀₀₁,Q₃₀₀₁, Q₃₀₀₁, Q₄₀₀₁ and Q₄₀₀₁ within the column switches C-SW1 to C-SW4.

Among the word lines WL₁₁ -WL₁₁₂₈, WL₂₁ -WL₂₁₂₈, WR₁₁ -WR₁₁₂₈ and WR₂₁-WR₂₁₂₈, one appointed by the combination of the external addresssignals A₀ -A₈ is selected by the row decoders R-DCR1 and R-DCR2described above. One complementary data line pair appointed by thecombination of the external address signals A₇, A₈, and A₉ -A₁₅ isselected from among a plurality of complementary data line pairs D₁₀₀₁,D₁₀₀₁ -D₁₁₂₈, D₁₁₂₈ ; D₂₀₀₁, D₂₀₀₁ -D₂₁₂₈, D₂₁₂₈ ; D₃₀₀₁, D₃₀₀₁ -D₃₁₂₈,D₃₁₂₈ ; and D₄₀₀₁, D₄₀₀₁ -D₄₁₂₈, D₄₁₂₈ by the column decoders C-DCR1 toC-DCR4 and the column switches C-SW1 to CSW4 described above. Thus, thememory cell M-CEL which is located at the intersection point between theselected word line and the selected complementary data line pair isselected.

In the reading operation, switching MISFETs Q₁ Q₁ -Q₄, Q₄, Q₈, Q₈, Q₁₂,Q₁₂, Q₁₆ and Q₁₆ are brought into "off" states by a control signal whichhas been delivered from the internal control signal generator circuitCOM-GE, though this is not especially restrictive. Thus, common datalines CDL₁, CDL₁ -CDL₄, CDL₄ and write signal input intermediateamplifiers DIIA1-DIIA4 are electrically isolated. The information of theselected memory cell is transmitted to the common data lines through theselected complementary data line pair. The information of the memorycell transmitted to the common data lines is sensed by the senseamplifier, and is delivered out through the data output intermediateamplifier DOIA as well as the data output buffer DOB.

In the present embodiment, sixteen sense amplifiers are provided. Amongthese sense amplifiers SA1-SA16, one sense amplifier, i.e., the senseamplifier whose input terminals are coupled to the selectedcomplementary data line pair through the common data lines, is selectedby a sense amplifier selection signal from the sense amplifier selectorcircuit SASC, and it executes the sensing operation.

In the writing operation, the switching MISFETs Q₁, Q₁ -Q₄, Q₄, Q₈, Q₈,Q₁₂, Q₁₂, Q₁₆ and Q₁₆ are brought into "on" states by the control signalfrom the internal control signal generator circuit COM-GE. In a casewhere the column decoder C-DCR1, for example, has brought the switchingMISFETs Q₁₀₀₁ and Q₁₀₀₁ into "on" states in accordance with the addresssignals A₇ -A₁₅, the output signal of the data input intermediateamplifier DIIA1 is transmitted to the complementary data line pairD₁₀₀₁, D₁₀₀₁ through the common data line pair DCL1, CDL1 and theMISFETs Q₁, Q₁, Q₁₀₀₁, Q₁₀₀₁. If, on this occasion, the word line WL11is selected by the row decoder R-DCR1, information corresponding tot heoutput signal of the data input intermediate amplifier DIIA1 is writteninto the memory cell which is disposed at the intersection point betweenthe word line WL11 and the complementary data lines D₁₀₀₁, D₁₀₀₁.

Although not especially restricted thereto, the common data line pairDCL1 and CDL1 is composed of four sets of common data line pairs(subcommon data line pairs) in the present embodiment. Among these foursets of common data line pairs, two sets of common data line pairs areshown in the figure. Likewise to the illustrated common data line pairs,the remaining two sets of common data line pairs are coupled to the datainput intermediate amplifier DIIA1 through the switching MISFETs Q₂, Q₂and Q₃, Q₃ respectively. The input terminals of one sense amplifier, andone input and output electrode of each of the 32 sets of switchingMISFETs are coupled to each of the four sets of common data line pairs.That is, the input terminals of the sense amplifier SA1 and the inputand output terminals of the switching MISFETs Q₁₀₀₁, Q₁₀₀₁ -Q₁₀₃₂, Q₁₀₃₂are coupled to the first common data line pair; the input terminals ofthe sense amplifier SA2 and the input and output terminals of theswitching MISFETs Q₁₀₃₃, Q₁₀₃₃ -Q₁₀₆₄, Q₁₀₆₄ are coupled to the secondcommon data line pair; the input terminals of the sense amplifier SA3and the input and output terminals of the switching MISFETs Q₁₀₆₅, Q₁₀₆₅-Q₁₀₉₆, Q₁₀₉₆ are coupled to the third common data line pair; and theinput terminals of the sense amplifier SA4 and the input and outputterminals of the switching MISFETs Q₁₀₉₇, Q₁₀₉₇ -Q₁₁₂₈, Q₁₁₂₈ arecoupled to the fourth common data line pair. In the writing operation,the four sets of common data line pairs are electrically coupled to eachother through the switching MISFETs Q₁, Q₁ -Q₄, Q₄, whereas in thereading operation, they are electrically isolated from each other. Thus,it is possible in the reading operation to reduce stray capacitanceswhich are coupled to the input terminals of the sense amplifier, so thatenhancement in the speed of the reading operation can be achieved. Inthe reading operation, only the sense amplifier having its inputterminals coupled to the subcommon data line pair to which theinformation from the selected memory cell has been transmitted throughthe switching MISFETs is selected to execute the sensing operation. Eachof the other common data line pairs CDL2, CDL2-CDL4, CDL4 has anarrangement similar to that of the common data line pair CDL, CDL1described above.

Although, in the present embodiment, the common control signal WECS issupplied to the switching MISFETs Q₁, Q₁ -Q₄, Q₄, Q₈, Q₈, Q₁₂, Q₁₂, Q₁₆and Q₁₆, the selection signals from the column decoders may well besupplied to the respective switching MISFETs. Thus, it is possible inthe writing operation to reduce the load capacitance of the data inputintermediate amplifier, so that enhancement in the speed of the writingoperation can be achieved.

The internal control signal generator circuit COM-GE receives twoexternal control signals, CS (chip select signal) and WE (write enablesignal), and generates a plurality of control signals CS₁, CS₂, CS₃,WECS, WECS, DOC, etc.

The sense amplifier circuit SASC receives the chip select signal CS andthe internal complementary address signals a₇ -a₁₅, and forms theforegoing sense amplifier selection signal and internal chip selectsignals CS, CS.

FIG. 2 is a block diagram which shows the address buffer ADB and rowdecoders R-DCR0, R-DCR1 and R-DCR2 in FIG. 2 in greater detail.

In FIG. 2, the circuits of those logic symbols whose output sides aremarked black are quasi-CMOS circuits wherein an output transistor forcharging and discharging an output signal line is made of a bipolartransistor, while transistors for logic processing such as inversion,non-inversion, NAND or NOR operations are made of CMOSFETs. The circuitof an ordinary logic symbol is a pure CMOS circuit.

As shown in FIG. 2, in the address buffer ADB, there are arrangednon-inverting/inverting circuits G₀ -G₈ whose inputs receive the addresssignals A₀ -A₈ of TTL levels from outside and which serve to transmitthe non-inverted outputs a₀ -a₈ and the inverted outputs a₀ -a₈ tocomplementary output signal lines.

Each of the non-inverting/inverting circuits G₀ =14 G₈ is constructed ofa quasi-CMOS circuit as shown in FIG. 4.

In FIG. 4, Q₄₀, Q₄₂, Q₄₄, Q₄₆, Q₅₀, Q₅₂ and Q₅₃ indicate N-channelMISFETs; Q₄₁, Q₄₃, Q₄₅ and Q₄₉ P-channel MISFETs; and Q₄₇, Q₄₈, Q₅₁ andQ₅₄ N-P-N bipolar transistors.

A resistor R₄₀ and the MISFET Q₄₀ constitute a gate protection circuitwhich serves to protect the gate insulator film of the MISFETs Q₄₁, Q₄₂from an external surge voltage applied to an input terminal.

Since the MISFETs Q₄₁, Q₄₂, Q₄₃ and Q₄₄ constitute a CMOS inverter oftwo-stage cascade connection, a signal inphase with the signal of a nodeN₁ is transmitted to a node N₃.

Since also the MISFETs Q₄₅ and Q₄₆ constitute a CMOS inverter, a signalantiphase to the signal of the node N₃ is transmitted to a node N₄.

The transistor Q₄₇ is an output transistor for charging the capacitiveload C₄₁ of an output terminal OUT, while the transistor Q₄₈ is anoutput transistor for discharging the capacitive load C₄₁.

Since also the MISFETs Q₄₉ and Q₅₀ constitute a CMOS inverter, a signalantiphase to the signal of the node N₃ is transmitted to a node N₅.

The MISFET Q₅₂ is a source-follower MISFET which is turned "on" by thesignal of the node N₃ so as to apply a base current to the transistorQ₅₄ for discharging the capacitive load C₄₂ of an output terminal OUT.The MISFET Q₅₃ operates, not only as the load of the source-followerMISFET Q₅₂, but also as a switching MISFET for discharging chargesstored in the base of the transistor Q₅₄.

In order to prevent the transistor Q₄₈ from being driven in itssaturation region, the source of the MISFET Q₄₅ is connected to thecollector of the transistor Q₄₈, not to a power source V_(CC). Likewise,in order to prevent the transistor Q₅₄ from being driven in itssaturation region, the drain of the MISFET Q₅₂ is connected to thecollector of the transistor Q₅₄, not to the power source V_(CC). Thispoint is also an important feature in improvements.

Accordingly, when a signal of high level is applied to the inputterminal IN in the non-inverting/inverting circuit of FIG. 4, the nodeN₃ becomes the high level, and the nodes N₄ and N₅ become a low level,to supply a base current to the base of the transistor Q₄₇ through thetransistor Q₄₃, so that the transistor Q₄₇ is turned "on". When theoutput terminal OUT is at the high level, the MISFET Q₅₂ is turned "on",so that the base current is supplied to the transistor Q₅₄ through thisMISFET Q₅₂. At this time, the MISFETs Q₄₆ and Q₅₀ are "on" because thenode N₃ is at the high level. In consequence, the transistors Q₄₅ andQ₅₄ turn "off" because charges stored in their bases are dischargedthrough the MISFETs Q₄₆ and Q₅₀. Therefore, the capacitive load C₄₁ ischarged rapidly by the bipolar output transistor Q₄₇ of low outputimpedance, while the capacitive load C₄₂ is discharged rapidly by thebipolar output transistor Q₅₄ of low output impedance. When the chargeof the capacitive load C₄₁ has ended, current stops flowing through thecollector-emitter path of the transistor Q₄₇. When the discharge of thecapacitive load C₄₁ has ended, currents stop flowing through thedrain-source path of the MISFET Q₅₂ and and the collector-emitter pathof the bipolar transistor Q₅₄.

When a signal of low level is applied to the input terminal IN of thenon-inverting/inverting circuit in FIG. 4, the transistors Q₄₇ and Q₅₄turn "off" and those Q₄₈ and Q₅₁ turn "on", so that the capacitive loadC₄₁ is discharged fast, while the capacitive load C₄₂ is charged fast.At this time, the MISFET Q₅₃ turns "on" because the node N₅ becomes thehigh level. In consequence, charges stored in the base of the bipolartransistor Q₅₄ are fast discharged to a ground potential point throughthe MISFET Q₅₃, so that the turn-off speed of the bipolar transistor Q₅₄is enhanced. When the discharge of the capacitive load C₄₁ has ended,currents stop flowing through the drain-source path of the MISFET Q₄₅and the collector-emitter path of the bipolar transistor Q₄₈. When thecharge of the capacitive load C₄₂ has ended, current stops flowingthrough the collector-emitter path of the bipolar transistor Q₅₁.

If the charge and discharge of the capacitive loads C₄₁ and C₄₂ are notexecuted by the bipolar output transistors Q₄₇, Q₄₈, Q₅₁ and Q₅₄ but areinstead executed by MISFETs, they will be executable only at low speedbecause the "on" resistance of the MISFET becomes a much larger value ascompared with that of the bipolar transistor.

In contrast, in the address buffer of the embodiment in FIG. 2, theoutput transistors of the non-inverting/inverting circuits G₀ -G₈ fordelivering the internal address signals a₀, a₀ -a₈, a₈ to the outputsignal lines thereof are made of the bipolar transistors as shown inFIG. 4, so that even when the output signal lines of thenon-inverting/inverting circuits G₀ -G₈ are arranged over relativelylong distances on the surface of the semiconductor chip, thenon-inverting/inverting circuits G₀ -G₈ are permitted to operate at highspeed.

The row decoder R-DCR0 in FIG. 2 operates as the predecoder of theaddress circuit. This row decoder R-DCR0 is constructed of 3-input NANDcircuits G₁₆ -G₂₃, G₂₄ -G₃₁ and G₄₀ -G₄₇ to which the internal addresssignals a₀, a₀ -a₈, a₈ obtained from the address buffer ADB are applied,and 2-input NOR circuits G₃₂ -G₃₉ to which the chip select signal CS andthe output signals of the 3-input NAND circuits G₂₄ -G₃₁ are applied.

The output signal lines (that is, the output signal lines of the 3-inputNAND circuits G₁₆ -G₂₃ and G₄₀ -G₄₇ and the output signal lines of the2-input NOR circuits G₃₂ -G₃₉) of the row decoder R-DCR0 as thepre-decoder are arranged over long distances in the vertical directionwithin the row decoders R-DCR1 and R-DCR2, which are the decoder driversof the address circuit, as illustrated in FIG. 2.

Each of the 3-input NAND circuits G₁₆ -G₂₃, G₂₄ -G₃₁ and G₄₀ -G₄₇ withinthe row decoder R-DCR0 in FIG. 2 is constructed of a quasi-CMOS circuitas shown in FIG. 5.

The quasi-CMOS 3-input NAND circuit in FIG. 5 includes an input logicprocessing portion which is composed of P-channel MISFETs Q₅₅ -Q₅₇ andN-channel MISFETs Q₅₈ -Q₆₁, and an output portion which is composed ofN-P-N bipolar output transistors Q₆₂, Q₆₃. The MISFET Q₆₁ operates as aswitching MISFET for discharging charges stored in the base of thebipolar transistor Q₆₃.

When input signals of high level are applied to all of three inputterminals IN₁ -IN₃, the transistors Q₅₅ -Q₅₇ turn "off", the transistorsQ₅₈ -Q₆₀ turn "on", a node N₇ becomes a low level, and the transistorQ₆₁ turns "off". Then, in the output portion, the transistor Q₆₂ turns"off", and when an output terminal OUT is at the high level, thetransistor Q₆₃ is supplied with a base current through the transistorsQ₅₈ -Q₆₀ and turns "on". Charges in the capacitive load C₄₃ of theoutput terminal OUT are rapidly discharged to a ground potential pointthrough the collector-emitter path of the transistor Q₆₃, while at thesame time, a discharge current flow through a route which extends alongthe capacitive load C₄₃, a diode Q₆₄, the MISFETs Q₅₈ -Q₆₀ and thebase-emitter junction of the bipolar transistor Q₆₃. A voltage dropacross both the ends of the diode Q₆₄ at this time controls thetransistor Q₆₂ into its "off" state reliably.

When an input signal of low level is applied to at least one of thethree input terminals IN₁ -IN₃, the node N₇ becomes the high level, thetransistor Q₆₂ turns "on", and the capacitive load C₄₃ is rapidlycharged through the collector-emitter path of the transistor Q₆₂.According to the high level of the node N₇, the transistor Q₆₁ turns"on", and the charges stored in the base of the transistor Q₆₃ arerapidly discharged through the drain-source path of the transistor Q₆₁,so that the turn-off speed of the transistor Q₆₃ can be enhanced.

In this manner, the output portion of the quasi-CMOS 3-input NANDcircuit in FIG. 5 is constructed of the bipolar transistors Q₆₂ and Q₆₃,and hence, the charge and discharge of the capacitive load C₄₃ areexecuted at high speed.

Incidentally, since the 3-input NAND circuits G₂₄ -G₃₁ within the rowdecoder R-DCR0 in FIG. 2 have their outputs connected to the inputs ofthe 2-input NOR circuits G₃₂ -G₃₉ which is only a relatively shortdistance connection, each of them may well be constructed of a pure CMOScircuit as shown in FIG. 6.

The pure CMOS 3-input NAND circuit in FIG. 6 is composed of P-channelMISFETs Q₆₄ -Q₆₆ and N-channel MISFETs Q₆₇ -Q₆₉. Since the length of asignal line from an output terminal OUT is short as described above, thecapacitance value of the stray capacitance C₄₄ of the output terminalOUT is small.

Accordingly, even when the charge and discharge of the small straycapacitance C₄₄ are executed by the MISFETs Q₆₄ -Q₆₆ and Q₆₇ -Q₆₉ havingcomparatively great "on" resistances, they can be executed atcomparatively high speed.

Each of the 2-input NOR circuits G₃₂ -G₃₉ within the row decoder R-DCR0in FIG. 2 is constructed of a quasi-CMOS circuit as shown in FIG. 7.

The quasi-CMOS 2-input NOR circuit in FIG. 7 includes an input logicprocessing portion which is composed of P-channel MISFETs Q₇₀, Q₇₁ andN-channel MISFETs Q₇₂ -Q₇₄, and an output portion which is composed ofN-P-N bipolar output transistors Q₇₅, Q₇₆. The MISFET Q₇₄ operates as aswitching MISFET which serves to discharge charges stored in the base ofthe bipolar transistor Q₇₆.

When input signals of low level are applied to both of two inputterminals IN₁ and IN₂, the transistors Q₇₀ and Q₇₁ turn "on", thetransistors Q₇₂ and Q₇₃ turn "off", and a node N₉ becomes a high level.Then, the transistor Q₇₅ turns "on", and the capacitive load C₄₅ of anoutput terminal OUT is rapidly charged through the collector-emitterpath of the transistor Q₇₅. The high level of the node N₉ turns "on" thetransistor Q₇₄, and the charges stored in the base of the transistor Q₇₆are rapidly discharged through the drain-source path of the transistorQ₇₄, so that the turn-off speed of the transistor Q₇₆ can be enhanced.

When an input signal of high level is applied to at least either of thetwo input terminals, for example, the input terminal IN₁, the transistorQ₇₀ turns "off", the transistor Q₇₂ turns "on", and the node N₉ becomesthe low level. Then, in the output portion, the transistor Q₇₅ turns"off", and when the output terminal OUT is at the high level, thetransistor Q₇₆ is supplied with a base current through the transistorsQ₇₂, Q₇₇ and turns "on". Charges in the capacitive load C₄₅ of theoutput terminal OUT are rapidly discharged through the collector-emitterpath of the transistor Q₇₆, while at the same time, a discharge currentflows through a route which extends along the capacitive load C₄₅, adiode Q₇₇, the drain-source path of the MISFET Q₇₂ and the base-emitterjunction of the bipolar transistor Q₇₆. Owing to a voltage drop acrossboth the ends of the diode Q₇₇ at this time, the bipolar transistor Q₇₅is reliably controlled into its "off" state.

The row decoders R-DCR1 and R-DCR2 in FIG. 2 operate as the decoderdrivers of the address circuit. The row decoder R-DCR1 includes a2-input NOR circuit G₄₈ which receives the output signals of the rowdecoder R-DCR0 2-input NAND circuits G₄₉ -G₅₆ which receive the outputsignal of the 2-input NOR circuit G₄₈ and the output signals of the rowdecoder R-DCR0, and inverters G₅₇ -G₆₄ which receive the output signalsof the 2-input NAND circuits G₄₉ -G₅₆.

The distances of the signal lines between the output of the 2-input NORcircuit G₄₈ and the inputs of the 2-input NAND circuits G₄₉ -G₅₆ arerelatively long, and the stray capacitance values of these signal linesare large. Accordingly, the 2-input NOR circuit G₄₈ is constructed ofthe quasi-CMOS circuit as shown in FIG. 7.

Since the 2-input NAND circuits G₄₉ -G₅₆ within the row decoder R-DCR1in FIG. 2 have their outputs connected to the inputs of the invertersG₅₇ -G₆₄ which is only a relatively short distance connection, each ofthem is constructed of a pure CMOS circuit as shown in FIG. 9.

The pure CMOS 2-input NAND circuit in FIG. 9 is composed of P-channelMISFETs Q₈₂, Q₈₃ and N-channel MISFETs Q₈₄, Q₈₅. Since the length of thesignal line from an output terminal OUT is short as described above, thecapacitance value of the stray capacitance of the output terminal OUT issmall.

Accordingly, even when the charge and discharge of the small straycapacitance C₄₇ are executed by the MISFETs Q₈₂, Q₈₃, Q₈₄ and Q₈₅ havingcomparatively great "on" resistances, they are executed at high speed.

The outputs of the inverters G₅₇ -G₆₄ within the row decoder R-DCR1 inFIG. 2 are connected to the word lines WL₁₁ -WL₁₈ of the memory arrayM-ARY1. Accordingly, the output signals lines (that is, the outputsignal lines of the inverters G₅₇ -G₆₄) of the row decoder R-DCR1 as thedecoder driver are arranged to cover relatively long distances in thelateral direction inside the memory array M-ARY1 as the word lines WL₁₁-WL₁₈, so that the stray capacitances of the word lines WL₁₁ -WL₁₈become quite large.

Thus, each of the inverters G₅₇ -G₆₄ within the row decoder R-DCR1 inFIG. 2 is constructed of a quasi-CMOS circuit as shown in FIG. 10.

The quasi-CMOS inverter in FIG. 10 is composed of a P-channel MISFETQ₈₆, N-channel MISFETs Q₈₇ -Q₈₉, and N-P-N bipolar output transistorsQ₉₀, Q₉₁. The operation of this quasi-CMOS inverter is the same as theoperation of the circuit Q₄₉ -Q₅₄ for obtaining the inverted output OUTof the non-inverting/inverting circuit in FIG. 4, and the detaileddescription shall therefore be omitted. The charge and discharge of agreat stray capacitance C₄₈ are executed at high speed by the N-P-Nbipolar output transistors Q₉₀, Q₉₁.

In FIG. 2, the row decoder D-DCR2 is constructed similarly to the R-DCR1stated above.

FIG. 3 is a block diagram which shows the address buffer ADB, the columndecoder C-DCR1, etc. in FIG. 1 in greater detail.

Also in FIG. 3, the circuits of those logic symbols whose output sidesare marked black are quasi-CMOS circuits wherein an output transistorfor charging and discharging the stray capacitance of an output signalline is made of a bipolar transistor and wherein logic processing suchas inversion, non-inversion, NAND or NOR is executed by a CMOS circuit.The circuit of an ordinary logic symbol is a pure CMOS circuit.

As shown in FIG. 3, in the address buffer ADB, there are arrangednon-inverting/inverting circuits G₇ -G₁₅ whose inputs receive theaddress signals A₇ -A₁₅ of TTL levels from outside and which serve totransmit the non-inverted output a₇ -a₁₅ and the inverted outputs a₇-a₁₅ to their complementary output signal lines.

Each of the non-inverting/inverting circuits G₇ -G₁₅ is constructed ofthe quasi-CMOS circuit as shown in FIG. 4. Accordingly, the outputtransistors of each of the non-inverting/inverting circuits G₇ -G₁₅ aremade of the bipolar transistors as illustrated in FIG. 4, so that evenwhen the output signal lines of the non-inverting/inverting circuits G₇-G₁₅ are arranged to extend relatively long distances on the surface ofthe semiconductor chip, the non-inverting/inverting circuits G₇ -G₁₅ arepermitted to operate at high speed.

The column decoder C-DCR1 includes 2-input NAND circuits G₇₄ -G₇₇, G₇₈-G₈₁ and G₈₂ -G₈₅ to which the internal address signals a₇ -a₁₅ and a₇-a₁₅ obtained from the address buffer ADB are applied, and 3-input NANDcircuits G₈₆ -G₉₃.

Further, as shown in FIG. 3, the output signal lines of the NANDcircuits G₇₄ -G₉₃ are arranged with long distances and are connected tothe input terminals of a large number of NOR circuits G₉₄ -G₉₅ insidethe column decoder C-DCR1, so that the stray capacitances of the outputsignal lines of the NAND circuits G₇₄ -G₉₃ become large capacitancevalues.

Accordingly, each of the 3-input NAND circuits G₈₆ -G₉₃ is constructedof the quasi-CMOS 3-input NAND circuit as shown in FIG. 5, and each ofthe 2-input NAND circuits G₇₄ -G₈₅ is constructed of a quasi-CMOS2-input NAND circuit which is obtained by omitting the input terminalIN₃ and the MISFETs Q₅₇, Q₆₀ from FIG. 5.

On the other hand, in FIG. 3, the output signal lines of the 3-input NORcircuits G₉₄, G₉₅ are connected to the inputs of inverters G₁₀₀, G₁₀₁with short distances, so that the stray capacitances of the outputsignal lines of the 3-input NOR circuits G₉₄ -G₉₅ have small capacitancevalues. Accordingly, each of the 3-input NOR circuits G₉₄ -G₉₅ isconstructed of a pure CMOS 3-input NOR circuit.

Further, the output signal lines of the inverters G₁₀₀, G₁₀₁ areconnected to the input terminals of 2-input NOR circuits G₉₈, G₉₉ with arelatively short distance connection so that the stray capacitances ofthe output signal lines of the inverters G₁₀₀ G₁₀₁ have smallcapacitance values. Accordingly, each of the inverters G₁₀₀, G₁₀₁ isconstructed of a well-known pure CMOS inverter.

Further, the output signal lines of the 2-input NOR circuits G₉₈, G₉₉are connected to the gate electrodes of the switching MISFETs Q₁₀₀₁,Q₁₀₀₁ of the column switch C-SW₁ with comparatively short distanceconnections, so that the stray capacitances of the output signal linesof the NOR circuits G₉₈, G₉₉ are small. Accordingly, each of these NORcircuits is constructed of a pure CMOS 2-input NOR circuit as shown inFIG. 8.

The pure CMOS 2-input NOR circuit in FIG. 8 is composed of P-channelMISFETs Q₇₈, Q₇₉ and N-channel MISFETs Q₈₀, Q₈₁. Since the distance ofthe signal line from an output terminal is comparatively short, thestray capacitance C₄₆ of the output terminal OUT has a small capacitancevalue.

Accordingly, even when the charge and discharge of the small straycapacitance C₄₆ are executed by the MISFETs Q₇₈, Q₇₉ Q₈₀ and Q₈₁ havingcomparatively great "on" resistances, they are executed at high speed.

Each of the aforementioned 3-input NOR circuits G₉₄ -G₉₅ is constructedof a pure CMOS 3-input circuit wherein a third input terminal IN₃ isadded to the 2-input NOR circuit in FIG. 8, a third P-channel MISFETwhose gate is connected to a third input terminal IN₃ is inserted inseries with the MISFETs Q₇₈ and Q₇₉, and a third N-channel MISFET whosegate is connected to the input terminal IN₃ is inserted in parallel withthe MISFETs Q₈₀, Q₈₁.

In addition to the above, it can be seen that, in FIG. 3, the 1-bitmemory cell M-CEL of the memory array M-ARY1 in FIG. 1 is shown ingreater detail. Specifically, the memory cell M-CEL is shown as beingcomposed of a flip-flop in which the inputs and outputs of a pair ofinverters consisting of load resistances R₁, R₂ and N-channel MISFETsQ₁₀₁, Q₁₀₂ are cross-connected, and N-channel MISFETs Q₁₀₃, Q₁₀₄ whichserve as transmission gates.

The flip-flop is employed as a means for storing information. Thetransmission gates are controlled by the address signal which is appliedto the word line WL₁₁ connected to the row decoder R-DCR1, and theinformation transmission between the complementary data line pair D₁₀₀₁,D₁₀₀₁ and the flip-flop is controlled by the transmission gates.

FIG. 11 is a circuit diagram in which one example of the essentialportions of the sense amplifier selector circuit SASC and one example ofthe internal control signal generator circuit COM-GE in FIG. 1 are shownmore in detail.

Shown in the figure is the circuit of that part of the sense amplifierselector circuit SASC which receives the external chip select signal CSand which forms the control signals CS, CS to be supplied to the dataoutput intermediate amplifier DOIA, the row decoder R-DCR0 and thecolumn decoder C-DCR1.

The circuit of this portion to which the external chip select signal CSis applied is constructed of the same circuit as thenon-inverting/inverting circuit in FIG. 4. Since the output signal CS ofthis circuit is obtained from bipolar output transistors R₁, T₂, T₃ andT₄, the capacitance dependences of the charging and discharging speedsof the outputs CS, CS of the sense amplifier selector circuit SASC arelow. Accordingly, even when the output CS of the sense amplifierselector circuit SASC is connected to the input terminals of the NORgates G₃₂ -G₃₉ of the row decoder R-DCR0 in FIG. 2 and to the inputterminals of the NOR gates G₉₄ -G₉₅ of the column decoder C-DCR1 in FIG.3, this output CS becomes fast. Besides, even when the output CS of thesense amplifier selector circuit SASC is connected to the gateelectrodes of a plurality of switching MISFETs within the data outputintermediate amplifier DOIA, this output CS becomes fast.

Although no illustration is made in the figure, the sense amplifierselector circuit SASC includes a decoder circuit which receives theinternal complementary address signals a₇ -a₁₅ and the aforementionedcontrol signal CS and which forms a selection signal S1 to be suppliedto the sense amplifier. Among the sense amplifiers SA1-SA16, the senseamplifier whose input terminals are electrically coupled to thecomplementary data line pair to be selected is selected by this decodercircuit, whereupon the sensing operation thereof is executed. The outputportion of this decoder circuit is constructed of a quasi-CMOS circuitso as to lower the capacitance dependences of the charge and dischargeof the output. Thus, the speed of the operation of selecting the senseamplifier can be enhanced. Even in a case where the above control signalis supplied to the decoder circuit, the control signal CS is fastbecause it is formed by the bipolar transistors as stated above.

Although, in the present embodiment, the decoder circuit is disposed inthe sense amplifier selector circuit SASC in order to select the senseamplifiers, the selection signals formed by the column decoders C-DCR1to C-DCR4 may well be utilized for the selection signals of the senseamplifiers. This measure can reduce the number of elements, andtherefore permits enhancing the density of integration.

The internal control signal generator circuit COM-GE in FIG. 11 includesa circuit portion which is supplied with the external chip select signalCS, thereby to generate a plurality of internal delay chip selectsignals CS₂, CS₁, CS₁ and CS₃. The greater part of this circuit portionis constructed of CMOS circuits. Since, however, the outputs CS₂, CS₁,CS₁ and CS₃ are respectively obtained from bipolar output transistorsT₅, T₆ ; T₉, T₁₀ ; T₁₁, T₁₂ ; and T₇, T₈, the capacitance dependences ofthe charge and discharge of these outputs are low.

The internal control signal generator circuit COM-GE in FIG. 11 isfurther provided with a circuit portion which is supplied with theexternal write enable signal WE and the internal delay chip selectsignals CS₁, CS₂, thereby to generate the write control signals WECS,WECS and a data output buffer control signal DOC. The greater part ofthis circuit portion is similarly constructed of CMOS circuits. Since,however, the signal WECS is obtained from bipolar output transistorsT₁₄, T₁₅, the capacitance dependences of the charge and discharge ofthis output WECS are low. Accordingly, even when the output WECS isapplied to the large number of input terminals of the NAND circuits (notshown) of the column decoder C-DCR1 in FIG. 3 or the gate electrodes ofthe switching MISFETs Q₁, Q₁₆ -Q₁₆, Q₁₆ in FIG. 1, this output WECSbecomes fast.

FIG. 12 is a circuit diagram in which the sense amplifier SA1, the dataoutput intermediate amplifier DOIA, the data output buffer DOB, etc, inFIG. 1 are shown more in detail.

FIG. 13 is a circuit diagram in which the data input buffer DIB, thedata input intermediate amplifier DIIA1, etc. in FIG. 1 are shown morein detail.

FIG. 14 is a diagram of the signal waveforms of various parts in theread cycle and write cycle of the static RAM which is one embodimentshown in FIGS. 1 to 13.

First, the operation of the static RAM in the cycle of readinginformation will be described with reference to FIGS. 12 and 14.

It is assumed that, as illustrated in FIG. 14, simultaneously with theapplication of the address signals A₀ -A₁₅, the chip select signal CS ischanged to the low level, whereas the write enable signal WE is held atthe high level as it is. As shown in FIG. 14, the internal delay chipselect signals CS₁, CS₂, CS₃, the write control signal WECS and the dataoutput buffer control signal DOC are produced from the internal controlsignal generator circuit COM-GE at that time.

In a case where the supplied address signals A₀ -A₁₅ are, for example,those which appoint the word line WL₁₁ and the complementary data linepair D₁₀₀₁, D₁₀₀₁, the memory cell M-CEL which is disposed at theintersection point between the word line WL₁₁ and the complementary dataline pair D₁₀₀₁, D₁₀₀₁ is selected. The internal information of theselected memory cell M-CEL is transmitted to both the inputs of thesense amplifier SA1 through the complementary data line pair D₁₀₀₁,D₁₀₀₁ and the switching MISFETs Q₁₀₀₁, Q₁₀₀₁. The sense amplifier SA1 iscomposed of a differential pair of emitter-coupled transistors T₂₁, T₂₂and a constant current source MISFET T₂₀. When the selection signal S1of high level is applied from the sense amplifier selector circuit SASCto the gate electrode of the constant current source MISFET T₂₀, thesense amplifier SA1 executes the sensing operation.

When the internal chip select signal CS of high level is applied fromthe sense amplifier selector circuit SASC to the gate electrodes ofconstant current source MISFETs T₂₃ -T₂₆ of the data output intermediateamplifier DOIA, this data output intermediate amplifier executes theamplifying operation.

Accordingly, the output signal of the sense amplifier SA1 is transmittedto the output node N₁₁ of the data output intermediate amplifier DOIAthrough grounded-base transistors T₂₇, T₂₈, emitter-follower transistorsT₂₉, T₃₀ and output MISFETs T₃₅ -T₃₈.

As illustrated in FIG. 12, the data output buffer DOB is supplied withthe data output buffer control signal DOC from the internal controlsignal generator circuit COM-GE. In addition, as shown in FIG. 12, thedata output buffer DOB is composed of a pure CMOS inverter of T₃₉ andT₄₀, a quasi-CMOS 2-input NAND circuit of T₄₁ -T₄₈, a quasi-CMOS 2-inputNOR circuit of T₄₉ -T₅₆, a P-channel switching MISFET T₅₇, an N-channelswitching MISFET T₅₈, a P-channel output MISFET T₅₉, and an N-channeloutput MISFET T₆₀.

When the data output buffer control signal DOC is at the high level, theswitching MISFETs T₅₇, T₅₈ are turned "on", and the output MISFETs T₅₉,T₆₀ are simultaneously turned "off", so that the output D_(out) of thedata output buffer DOB falls into a high impedance state (floatingstate).

In the cycle of reading information, the data output buffer controlsignal DOC becomes the low level to turn "off" the switching MISFETsT₅₇, T₅₈, and the gate electrodes of the output MISFETs T₅₉, T₆₀ arecontrolled by the output of the quasi-CMOS 2-input NAND circuit and theoutput of the quasi-CMOS 2-input NOR circuit, the outputs beingresponsive to the signal level of the output node N₁₁ of the data outputintermediate amplifier DOIA, whereby valid data is obtained from theoutput terminal D_(out).

In order to reduce the "on" resistances of the output MISFETs T₅₉, T₆₀,the channel widths W of these MISFETs are set at very large values.Then, the gate capacitances of these MISFETs T₅₉, T₆₀ become very large.Since, however, the output portion of the quasi-CMOS 2-input NANDcircuit is composed of the bipolar output transistors T₄₇, T₄₈ and theoutput portion of the quasi-CMOS 2-input NOR circuit is composed of thebipolar output transistors T₅₅, T₅₆, the charge and discharge of thegate capacitances of the output MISFETs T₅₉, T₆₀ are executed at highspeed.

Referring now to FIGS. 13 and 14, the operation of the static RAM in thecycle of writing information will be described.

As illustrated in FIG. 14, simultaneously with the application of theaddress signals A₀ -A₁₅, the chip select signal CS changes to the lowlevel, whereupon the write enable signal WE changes to the low level. Asshown in FIG. 14, the internal delay chip select signals CS₁, CS₂, CS₃,the write control signal WECS and the data output buffer control signalDOC are produced from the internal control signal generator circuitCOM-GE at that time.

As shown in FIG. 13, input data D_(in) and the inverted internal chipselect signal CS₁ are applied to the data input buffer DIB. In writinginformation, the signal CS₁ changes to the low level. Then, a P-channelswitching MISFETT₆₁ of the data input buffer changes into the "on"state, and an N-channel switching MISFET T₆₂ into the "off" state. Thus,the input data D_(in) is transmitted to an output node N₁₂ through pureCMOS inverters in multi-stage connection.

In writing information, the write control signal WECS changes to the lowlevel. Then, within the data input intermediate amplifier DIIA1 in FIG.13, P-channel MISFETs T₆₃, T₆₅ turn "on", and N-channel MISFETs T₆₄, T₆₆turn "off", so that a signal inphase with the signal of the output nodeN₁₂ of the data input buffer DIB appears at a node N₁₃, while a signalantiphase thereto appears at a node N₁₄.

The signal of the node N₁₃ is transmitted to the common data line CDL₁through a quasi-CMOS inverter composed of transistors T₆₇ -T₇₂, whilethe signal of the node N₁₄ is transmitted to the common data line CDL₁through a quasi-CMOS inverter composed of transistors T₇₃ -T₇₈. Sincethe charge and discharge of the common data line pair CDL₁, CDL₁ ofgreat parasitic capacitances are executed by the bipolar outputtransistors T₇₁, T₇₂ and T₇₇, T₇₈ of these quasi-CMOS inverters, theyare executed at high speed.

Thus, the complementary output signals of the data input intermediateamplifier DIIA1 are transmitted to the memory cell M-CEL through thecommon data line pair CDL₁, CDL₁, the switching MISFETs Q₁, Q₁, Q₁₀₀₁,Q₁₀₀₁, and the complementary data line pair D₁₀₀₁, D₁₀₀₁, whereby thewriting of the information into the memory cell is executed.

As a result of the structure described in the foregoing description, thefollowing advantages are achieved:

(1) Each of the non-inverting/inverting circuits G₀ -G₁₅ of an addressbuffer ADB is constructed of a quasi-CMOS circuit. Since, in thequasi-CMOS circuit, the greater part of a logic processing portion ofnon-inversion/inversion is constructed of CMOS circuits, a low powerconsumption is possible. Further, output transistors which execute thecharge and discharge of non-inverted and inverted outputs are made ofbipolar transistors, so that even when the stray capacitances of theoutput signal lines of the non-inverting/inverting circuits G₀ -G₁₅become large, a high speed operation is obtained since the bipolartransistors can afford a lower output resistance with smaller elementdimensions than a MISFET.

(2) Circuits whose output signal lines have large stray capacitances,such as the NAND circuits G₁₆ -G₂₃, G₂₄ -G₃₁, G₄₀ -G₄₇, the NOR circuitsG₃₂ -G₃₉, G₄₈ -G₆₅ and the inverters G₅₇ -G₆₄ of row decoders R-DCR0,R-DCR1, R-DCR2 are constructed of quasi-CMOS circuits, so that thesecircuits will be low in the power consumption and high in operatingspeed.

Further, circuits whose output signal lines have small straycapacitances, such as NAND circuits G₄₉ -G₅₆, are constructed of pureCMOS circuits, so that these circuits can be low in the powerconsumption.

(3) Circuits whose output signal lines have large stray capacitances,such as the NAND circuits G₇₄ -G₉₃ of column decoders C-DCR1 to C-DCR4,are constructed of quasi-CMOS circuits, so that these circuits will below in the power consumption and high in operating speed.

Further, circuits whose output signal lines have small straycapacitances, such as NOR circuits G₉₄ -G₉₉ and inverters G₁₀₀, G₁₀₁,are constructed of pure CMOS circuits, so that these circuits will below in the power consumption.

(4) Since a non-inverting/inverting circuit constituting a senseamplifier selector circuit SASC is constructed of a quasi-CMOS circuit,a low power consumption is achieved. Also, since outputs CS, CS areobtained from bipolar output transistors, these outputs CS, CS becomefast even when their stray capacitances are large.

(5) Since an internal control signal generator circuit COM-GE isconstructed of a quasi-CMOS circuit, a low power consumption isachieved, and since outputs CS₂, CS₃, CS₁, CS₁, WECS are obtained frombipolar output transistors, these outputs CS₂, CS₃, CS₁, CS₁, WECSbecome fast even when their stray capacitances are large.

(6) Since a data output buffer DOB is constructed of a quasi-CMOScircuit, a low power consumption is achieved.

Further, since the large gate capacitances of the output MISFETs of thedata output buffer DOB are charged and discharged by bipolar outputtransistors, the charge and discharge of the gate capacitances areexecuted at high speed.

(7) Since a data input buffer DIB is constructed of a pure CMOS circuit,a low power consumption is achieved.

(8) Since a data input intermediate amplifier DIIA1 is constructed of aquasi-CMOS circuit, a low power consumption is achieved.

Further, since the charge and discharge of common data line pair CDL₁,CDL₁, which have large parasitic capacitances, are executed by bipolaroutput transistors, they are executed at high speed.

Owing to the synergistic effect of the above, the followingcharacteristics could be obtained in the static SRAM described in theforegoing embodiment:

(a) The propagration delay time t_(pd) from the input to the output ofeach of the non-inverting/inverting circuits G₀ -G₁₅ of the addressbuffer ADB was shortened to about 3.0 (nsec). The stand-by powerconsumption of all the non-inverting/inverting circuits G₀ -G₁₅ wasreduced to about 33.7 (mW), and the operating power consumption to about45.8 (mW).

(b) The propagation delay time t_(pd) from the input to the output ofeach of the row decoders R-DCR0, R-DCR1, R-DCR2 and the column decodersC-DCR1 to C-DCR4 was reduced to about 4.8 (nsec). The stand-by powerconsumption of all the decoders was reduced to substantially zero, andthe operating to about 153 (mW).

(c) The propagation delay time t_(pd) of all of a memory cell M-CEL, asense amplifier SA1 and a data output intermediate amplifier DOIA wasreduced to about 5.0 (nsec). The stand-by power consumption of allmemory cells M-CEL numbering 64 k (65536), all sense amplifiersSA1-SA16, and the data output intermediate amplifier DOIA was reduced toabout 0.6 (mW), and the operating power consumption to about 160 (mW).

(d) The propagation delay time t_(pd) from the input to the output ofthe data output buffer DOB was shortened to 2.8 (nsec). The stand-bypower consumption was reduced to substantially zero, and the operatingpower consumption to 23.5 (mW).

(e) Owing to the above (a)-(d), the access time (read time) wasshortened to about 15.6 (nsec). This value is substantially equal to the15 (nsec) access time of presently known ECL type bipolar RAMs.

(f) Owing to the above (a)-(d), the stand-by power consumption of thestatic SRAM of the present embodiment was reduced to about 34.3 (mW),and the operating power consumption to about 382.3 (mW). These valuesrepresent relatively low power consumption characteristics intermediatebetween those of a prior-art bipolar RAM and a prior-art static MOSRAM(and actually closer to those of the prior-art static MOSRAM).

Although, in the above, the invention made by the inventors has beenconcretely described on the basis of a preferred embodiment, it isneedless to say that the present invention is not restricted to theforegoing embodiment. On the contrary, it can be variously modifiedwithin a scope not departing from the subject matter thereof.

For example, in the memory cell M-CEL in FIG. 3, the load resistancesR₁, R₂ may well be replaced with P-channel MISFETs so as to constructthe flip-flop out of CMOS inverters. Besides, the flip-flop may well beconstructed of multi-emitter N-P-N transistors.

Further, by performing refresh, the memory cell M-CEL may well beconstructed of an information latch circuit based on the storage ofcharges in a cell capacitance, not of the flip-flop circuit.

The signal level of the address signals A₀ -A₁₅ which are applied to theaddress buffer ADB may well be set to be ECL levels, rather than TTLlevels, with the address buffer ADB executing a proper level conversionoperation.

An input D_(in) or output D_(out) may well be constructed in the form ofa plurality of bits (for example, 4 bits, 8 bits, . . . ), not 1 bit.

Also, of course, the number of the memory matrices is not restricted tofour, but it may well be larger or smaller.

Further, although specific values have been given for various parameterson characteristics, it is to be understood that these are illustrativeonly, and do not serve to limit the present invention.

Finally, while , in the above, the invention made by the inventors hasbeen chiefly described as to the case of application to thesemiconductor memory, it is not restricted thereto.

For example, it is needless to say that, not only memory cells, addresscircuits for selecting a specified cell, signal circuits for handlingthe reading and writing of information, and the timing circuits forcontrolling the operations of reading and writing information canutilize the present invention. On the contrary, a variery of othercircuits such as bipolar analog circuits, MOS analog circuits, P-channelMOS logic, N-channel MOS logic, CMOS logic, I² L circuits and ECLcircuits can be arranged on the semiconductor chip as may be needed toincorporate the principles of the present invention.

We claim:
 1. A semiconductor integrated circuit device, on a singlesemiconductor chip, comprising:a memory array including a plurality ofmemory cells comprised of MISFETs; and a decoder circuit coupled toreceive address signals and for decoding the address signals to selectat least one memory cell in the memory array, the decoder circuitincluding:a first decoder circuit serving as a predecoder and coupled toreceive the address signals at inputs thereof, and including means forproviding decoded signals at outputs thereof, the first decoder circuitbeing provided on the semiconductor chip so as to be separated from thememory array by a predetermined spacing, the first decoder circuitincluding an output stage for providing the decoded signals, and asecond decoder circuit coupled by signal lines to the output stage ofthe first decoder circuit to receive the decoded signals at inputsthereof, and including means for providing output signals to the memoryarray, the second decoder circuit being provided on the semiconductorchip so as to be closer to the memory array than said first decodercircuit is, wherein said output stage of said first decoder circuit iscomprised of bipolar output transistors to permit rapid charging anddischarging of stray capacitance at the output of said first decodercaused by said signal lines between the output stage of the firstdecoder circuit and the inputs of the second decoder circuit, so thatsaid decoder circuit can operate at high speed.
 2. A semiconductorintegrated circuit device according to claim 1, wherein each of theplurality of memory cells is a memory cell for a random access memory.3. A semiconductor integrated circuit device according to claim 2,wherein each memory cell for the random access memory includes aflip-flop circuit, and wherein the MISFETs in the memory cells for therandom access memory are P- and N-channel MISFETs forming the flip-flopcircuits.
 4. A semiconductor integrated circuit device according toclaim 2, wherein each memory cell for the random access memory includesa flip-flop circuit, wherein the MISFETs in each memory cell for therandom access memory are of an N-channel type, and wherein each memorycell for the random access memory further includes at least oneresistance element of polycrystalline silicon to form the flip-flopcircuit in conjunction with the N-channel MISFETs.
 5. A semiconductorintegrated circuit device according to claim 2, wherein the firstdecoder circuit includes an input stage comprised of P- and N-channelMISFETs and the output stage.
 6. A semiconductor integrated circuitdevice according to claim 2,wherein the second decoder circuitincludes:a row decoder corresponding to rows of the memory array, and acolumn decoder corresponding to columns of the memory array, and whereinthe first decoder circuit includes:a decoder corresponding to the rowdecoder, and a decoder corresponding to the column decoder.
 7. Asemiconductor integrated memory circuit device, on a singlesemiconductor chip, comprising:a memory array including a plurality ofmemory cells comprised of MISFETs, a plurality of word lines and aplurality of pairs of data lines coupled to the plurality of memorycells so that each memory cell is coupled to one word line and to onepair of data lines; and a decoder circuit coupled to receive addresssignals and including means for decoding the address signals to selectat least one memory cell in the memory array by selecting at least oneword line and at least one pair of data lines, the decoder circuitincluding:a first decoder circuit serving as a predecoder and coupled toreceive the address signals at inputs thereof, and including means forproviding decoded signals at outputs thereof, the first decoder circuitincluding an output stage for providing the decoded signals, the firstdecoder circuit being arranged on the semiconductor chip so as to beseparated from the memory array by a predetermined spacing, and a seconddecoder circuit coupled by signal lines to the output stage of the firstdecoder circuit to receive the decoded signals at inputs thereof, andincluding means for providing output signals, the second decoder circuitbeing arranged on the semiconductor chip so as to be closer to thememory array than said fist decoder circuit is wherein said output stageof said first decoder circuit is comprised of bipolar output transistorsto permit rapid charging and discharging of stray capacitance at theoutput of said first decoder caused by said signal lines between theoutput stage of the decoder circuit and the inputs of the second decodercircuit, so that said first decoder circuit can operate at high speed.8. A semiconductor integrated memory circuit device according to claim7, wherein each of the plurality of memory cells is a memory cell for astatic random access memory.
 9. A semiconductor integrated memorycircuit device according to claim 8, wherein each memory cell for thestatic random access memory includes a flip-flop circuit, and whereinthe MISFETs in the memory cells for the random access memory are P- andN-channel MISFETs forming the flip-flop circuits.
 10. A semiconductorintegrated memory circuit device according to claim 8, wherein eachmemory cell for the static random access memory includes a flip-flopcircuit, wherein the MISFETs in each memory cell for the static randomaccess memory are of an N-channel type, and wherein each memory cell forthe static random access memory further includes at least one resistanceelement of polycrystalline silicon to form the flip-flop circuit inconjunction with the N-channel MISFETs.
 11. A semiconductor integratedmemory circuit device according to claim 7, wherein the first decodercircuit includes an input stage comprised of P- and N-channel MISFETsand the output stage.
 12. A semiconductor integrated memory circuitdevice according to claim 7,wherein the second decoder circuitincludes:a row decoder corresponding to rows of the memory array, and acolumn decoder corresponding to columns of the memory array, and whereinthe first decoder circuit includes:a decoder corresponding to the rowdecoder, and a decoder corresponding to the column decoder.
 13. Asemiconductor integrated memory circuit device, on a singlesemiconductor chip, comprising:a memory array including a plurality ofmemory cells comprised of MISFETs, a plurality of word lines and aplurality of pairs of data lines coupled to the plurality of memorycells so that one memory cell is coupled to one word line and to onepair of data lines; an address buffer circuit coupled to receive addresssignals and for providing internal address signals; and a decodercircuit coupled to receive the internal address signals and for decodingthe internal address signals to select at least one memory cell in thememory array by selecting at least one word line and at least one pairof data lines, the decoder circuit including: a first decoder circuitserving as a predecoder and coupled to receive the address signals atinputs thereof and for providing output signals at outputs thereof, thefirst decoder circuit including an output stage for providing the outputsignals, respectively, a second decoder circuit coupled to receive theoutput signals of the first decoder circuit at inputs thereof and forproviding decode output signals at outputs thereof, the outputs of thesecond decoder circuit being coupled to the word lines, respectively,and a plurality of signal lines coupled between the outputs of the firstdecoder circuit and the inputs of the second decoder circuit,respectively, and for delivering the output signals of the first decodercircuit to the inputs of the second decoder circuit, the plurality ofsignal lines being arranged over long distances on the singlesemiconductor chip, wherein said output stage of said first decodercircuit is comprised of bipolar output transistors to permit rapidcharging and discharging of stray capacitance at the output of saidfirst decoder caused by said signal lines between the output stage ofthe first decoder circuit and the inputs of the second decoder circuitso that said decoder circuit can operate at high speed.
 14. Asemiconductor integrated memory circuit device according to claim 13,wherein each of the plurality of memory cells is a memory cell for astatic random access memory.
 15. A semiconductor integrated memorycircuit device according to claim 14, wherein the memory cell for thestatic random access memory includes a flip-flop circuit, and whereinthe MISFETs in the memory cell for the static random access memory areP- and N-channel MISFETs forming the flip-flop circuit.
 16. Asemiconductor integrated memory circuit device according to claim 14,wherein the memory cell for the static random access memory includes aflip-flop circuit, wherein the MISFETs in the memory cell for the randomaccess memory are of an N-channel type, and wherein the memory cell forthe static random access memory further includes resistance elements ofpolycrystalline silicon to form the flip-flop circuit in conjunctionwith the N-channel MISFETs.
 17. A semiconductor integrated memorycircuit device according to claim 13, wherein the first decoder circuitincludes an input stage comprised of P- and N-channel MISFETs and theoutput stage.
 18. A semiconductor integrated memory circuit deviceaccording to claim 13, wherein the second decoder circuit includes aninput stage comprised of P- and N-channel MISFETs having gates thereofcoupled to the plurality of signal lines.
 19. A semiconductor integratedmemory circuit device according to claim 18, wherein the second decodercircuit includes an output stage comprised of bipolar transistorscoupled to the plurality of word lines.
 20. A semiconductor integratedmemory circuit device according to claim 13, wherein the memory arrayincludes first and second arrays, wherein the second decoder circuit isarranged between the first and second arrays, and wherein the firstdecoder circuit is not arranged between the first and second arrays. 21.A semiconductor integrated circuit device according to claim 1, whereinsaid signal lines between the output stage of the first decoder circuitand the input of the second decoder circuit are arranged over longdistances on the single semiconductor chip.
 22. A semiconductorintegrated circuit device according to claim 21, wherein the memoryarray includes first and second arrays, wherein the second decodercircuit is arranged between the first and second arrays, and wherein thefirst decoder circuit is not arranged between the first and secondarrays.
 23. A semiconductor integrated circuit device according to claim22, wherein the second decoder circuit includes an input stage comprisedof P- and N-channel MISFETs having gate electrodes coupled to theplurality of signal lines.
 24. A semiconductor integrated circuit deviceaccording to claim 22, wherein the second decoder circuit includes anoutput stage comprised of bipolar transistors for outputting the outputsignals.
 25. A semiconductor integrated memory circuit device accordingto claim 7, wherein the second decoder circuit includes an output stagecomprised of bipolar transistors coupled to the plurality of word lines.26. A semiconductor integrated memory circuit device according to claim25, wherein the memory array includes first and second arrays, whereinthe second decoder circuit is arranged between the first and secondarrays, and wherein the first decoder circuit is not arranged betweenthe first and second arrays.
 27. A semiconductor integrated memorycircuit device according to claim 7, wherein said signal lines betweenthe output stage of the first decoder circuit and the input of thesecond decoder circuit are arranged over long distances on the singlesemiconductor chip.
 28. A semiconductor integrated memory circuit deviceaccording to claim 27, wherein the memory array includes first andsecond arrays, wherein the second decoder circuit is arranged betweenthe first and second arrays, and wherein the first decoder circuit isnot arranged between the first and second arrays.
 29. A semiconductorintegrated memory circuit device according to claim 28, wherein thesecond decoder circuit includes an input stage comprised of P- andN-channel MISFETs having gate electrodes coupled to the plurality ofsignal lines.
 30. A semiconductor integrated memory circuit deviceaccording to claim 28, wherein the second decoder circuit includes anoutput stage comprised of bipolar transistors for outputting the outputsignals.